A critical parameter in the design of insulated gate semiconductor devices such as insulated gate field effect transistors (e.g., MOSFETs) and insulated gate bipolar transistors (IGBTs) is the forward on-state resistance because it determines the maximum current rating of the device. With respect to power MOSFETs, the on-state resistance is the total resistance between the source and drain terminals during forward conduction. This total resistance can be determined by summing the resistance contributions of the MOSFET's source region, channel region, accumulation region (which accounts for current spreading), JFET region, drift region and drain/substrate region. Determination of the total resistance for DMOS-type power MOSFETs is more fully described and illustrated in section 7.4.4 of a textbook by B. J. Baliga entitled Power Semiconductor Devices, PWS Publishing Co. (ISBN 0-534-94098-6) (1995).
However, while it may be advantageous to reduce the resistance of each of these regions to minimize forward on-state resistance, the resistance of the drift region generally cannot be minimized without significantly reducing the breakdown voltage of the device. Thus, to reduce on-state resistance, attempts have typically focused on reducing the resistance of the JFET and accumulation region by doping both these regions to relatively high levels. For example, U.S. Pat. No. 4,680,853 to Lidow et al. discloses a power MOSFET having a highly doped JFET and accumulation region 130 which is formed by performing a blanket implant of phosphorus ions at a dose in the range of 1.times.10.sup.11 to 1.times.10.sup.14 atoms/cm.sup.2. Unfortunately, such blanket implant can reduce the punch-through voltage of the devices, adversely effect the characteristics of the channel region and reduce control over obtaining preselected threshold voltages. A prior art power MOSFET which is similar to FIG. 22 of the '853 patent to Lidow et al. is disclosed at FIG. 1. This power MOSFET includes a drain region 10, drift region 20, accumulation region 100 and JFET region 200 (shown collectively as region 22), base region 50, source region 52, source contact 72, drain contact 74 and insulated gate electrode (regions 60-80). FIG. 3A also discloses a prior art substrate which can be used to form the device of FIG. 1.
Thus, notwithstanding the above described attempts to improve performance of insulated gate semiconductor devices such as power MOSFETs, there continues to be a need for devices which have both low on-state resistance and high punch-through and breakdown voltages and can be formed without loss of control over device threshold voltage.